Clock recovery devices have been widely used in display drivers and communication circuits. Exemplary clock recovery devices include a delay locked loop (DLL) and a phase locked loop (PLL). A DLL is an electronic circuit that takes an input signal and outputs multiple phase delayed signals. A PLL is an electronic circuit which typically includes a voltage controlled oscillator that is constantly adjusted to match the frequency of an input clock signal. Circuits include DLLs and PLLs may operate in a low power sleep mode in order to save power consumption. However, DLLs and PLLs require a certain amount of time to stabilize and acquire a feedback lock on the input signal. Such transient lock time may become a significant period in modern high speed circuits. Thus there is a need for a fast relocking mechanism when circuits including DLLs or PLLs exit the low power sleep mode.